Chronologic VCS simulator copyright 1991-2020
Contains Synopsys proprietary information.
Compiler version R-2020.12-1_Full64; Runtime version R-2020.12-1_Full64;  Oct 12 15:15 2023
[UART] UART0 is here (stdin/stdout).
C0: reg block 4x5x6, cache block 40x50x60
mcycle = 216284
minstret = 191795
$finish called from file "/proj/users/hanwei.fan/dataset/generated-src/chipyard.harness.TestHarness.Boom64n8n256n8n2n3n128n2n1n1n4/gen-collateral/TestDriver.v", line 158.
$finish at simulation time           5990865500
           V C S   S i m u l a t i o n   R e p o r t 
Time: 5990865500 ps
CPU Time:   1534.250 seconds;       Data structure size:   3.1Mb
Thu Oct 12 15:41:31 2023
